Hello,
When producing clocks (for ADC) for AFE5801, do you see any issue with using FPGA to create the clock? I am using Xilinx Spartan-3. The FPGA uses clocks from a PLL (CY68013A), however, I am not sure what the jitter is like if I FPGA uses that clock to generate another clock. I know this is hard to answer without me providing any real values (jitter, etc.) but I am looking for some intuitions from the ultrasound experts...
The evaluation board uses another chip to create the clock, but I was hoping if I can synchronize the clock with my "system" clock so that I can control easily when to turn on/off AFE ADC clock as well as control number of cycles and such. This is pretty trivial if I use the FPGA, but not sure if ADC performance will be degraded too much.
Thanks in advance for the help!
John