Hi Martin, Jim has reviewed your questions and sent me the following responses to your questions: "The timing between PHIA1 and SH1 doesn’t match the CIS sensor datasheet exactly, but it does meet the listed timing requirements: To enable SH2 as the data clock, Page 0, Register 5 should be set to 0xE0. To enable Slave mode he needs to set Page 0 Register 0 to 0x20 and then to 0x21. Then start applying the SH_R pulses from the FPGA. If these aren’t working then he should double check that his writes are going through by reading back the values before and after the write. His sensor is CIS with 3 lamp colors (R, G, B) and 3 analog outputs. If the LM98725 was driving the lamp controls, for color scanning he should be using CISa or CISb with a 3 line sequence. Since the FPGA is controlling the lamps he can just use normal Mode 3 and a single SH sequence. The FPGA will know which color data is now being output by the AFE since it knows when the R, G or B lamps are turned on. So Page 2 Register 10h should be set to 0x00h. There are test pattern modes available that can verify the data path is working OK. To enable test pattern first clear the Lock Bit, then set the following: Page 0, Register 6 = 0x01h or 0x09h. These are both ramp patterns, once with the code increasing at the pixel rate, the other increasing at the SH interval rate. Once that is set, then set the Lock Bit. From this register there are other test patterns that can be enabled and might also be useful." Regards, Hooman
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