Hello Martin, I'd like to ask you for these waveforms to help us diagnose your issues: 1. Waveform showing SH_R, SP, and CP waveforms together. 2. Zoomed in view of SH_R and CP. 3. Zoomed in view of CP and SP. Regarding your question of why you can get Test Patterns to show at output but not the CSI data: This could be related to the amplitude, gain, and offset of the input channels relative to where the AFE expects these to be. Setting the gain to minimum might be one way to ensure you are not overdriving the internal ADC's. Manipulating the offsets would be another way to see if you can get valid data. Your VCLP pin in your schematic is left floating which means you must use register Page 0, Address 4, bits [2:0] to a VCLP value below the minimum CIS sensor output. Furthermore, you must ensure that the Sample and Clamp pulses are occurring at the correct time within your sensor output, similar to what Figure 28 shows. For that, you can use the feature of Page 0, Address 21, bits [2:0} (Sample and Clamp Monitor) where you can send the Sample, and Clamp pulses to SH3 to make sure they coincide with your sensor output. In your case, you'd want the same value for Sample, and Clamp for all 3 RGB signals. You monitor SH3 and sensor output simultaneously and adjust the register until you coincide with the active portion of the waveform. Use Page 0, Address 8 through Address 19 (Sample and Clamp Start and Stop Edge) to move the Sample and Clamp pulses for proper line up. Keep in mind that there is a couple of ns of delay between actual internal signals and what the "monitor" output shows on SH3. Once you get in the ballpark, you would then move the values around slightly and look for the lowest noise for optimization. Also, please update your schematic and register values, if they have been changed, the next time you post. Regards, Hooman
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