Hi Everybody,
When clocking the AFE5808 40MSPS everything is fine. However, at 60MSPS the output from FPGA becomes a (unintended) perfect random number generator-:)
Could anybody share the 12/14bit wide deserializer solution for Spartan-6? 99% I'm sure the problem is in timing inside of the FPGA. PCB routing and LVDS termination seems to be OK.
Thanks, Mariusz