Forum Post: RE: Deserializing AFE5808 data on Spartan-6 FPGA

Hi Chuck,

Ooopss, I've just clicked wrong button..  In fact, the problem is still 'alive'. I've made some tricks on timing costraint on FPGA. Works @65MSPS a little better, some bits are stable, some not!!  For sure, the problem is not on the TI , also not on a Xilinx !!  The Virtex deserializer source files (VHDL/Verilog) will be very welcome for all the groupers!!

Thanks,

Mariusz