Hi Rom If you've only written to those registers on page 0 and page 8, the CCD Timing outputs won't be providing useful clocking. Please try loading the following register settings (followed by setting the register lock bit) to see if that changes the waveforms see on the outputs. /cfs-file/__key/communityserver-discussions-components-files/239/CIS-Example-Mode-1-one-color-sequence.dat Changes made: Enable CMOS data clock at SH12 (Page 0 Register 5 Bit 5) Setting sample and clamp timing to values in-range for Mode 1, Sample and Hold (Page 0 Registers 08 to 13h). Enable one SH interval for 15 clocks (Page 3 Register 0) Set SH1 high during SH interval 1 (Page 5 Register 0 bit 0) Setting PHIA, PHIB and RS and CP on/off timing for 50% duty cycle (Page 6 Registers 00 to 1Dh) Make SH1 turn on at pixel 500 and off at pixel 1000 (Page Registers 00-03h) The file format doesn't include a Page number, but instead has all registers in series with each page being 1F registers long. Best regards, Jim B
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