Hi Reggie! Welcome to our e2e Forum! Can you include those logic analyzer plots? One thing you are missing I believe is the command bytes, you need to account for those as well. The MCLK along with the data rate setting (OSR of 32 in your case I assume) sets up the period between DRDY active transitions (720kHz/32 = 22.5kHz in your setup). What happens if you boost up your SCLK to something like 2MHz?
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