Part Number: DDC112 Thanks for your reply. 1.After check:My VREF is very good,and the chip and circuit is the same as the datasheet. 2.My DCKL frequency is 9MHz, it is created by stm32F1 SPI peripheral and 8Xprescaled from 72MHz to 9MHz. 3.My DDC112 range setting is rang1(12.5pF). 4.My data result using TEST mode as below test condition:(1.two channel and unit is fA; 2.Integrating time is 1000ms; 3.range1;): ch1:13628.01 ch2:13628.11fA ch1:13397.00 ch2:13402.51fA ch1:13628.44 ch2:13629.47fA ch1:13397.80 ch2:13402.84fA ch1:13627.92 ch2:13628.95fA ch1:13396.72 ch2:13403.21fA ch1:13628.53 ch2:13628.15fA ch1:13396.58 ch2:13402.18fA ch1:13627.97 ch2:13629.75fA ch1:13397.10 ch2:13403.12fA ch1:13628.58 ch2:13629.90fA ch1:13397.85 ch2:13402.22fA ch1:13627.50 ch2:13628.86fA ch1:13397.00 ch2:13401.33fA ch1:13627.97 ch2:13629.24fA ch1:13397.52 ch2:13402.93fA test condition:(1.two channel and unit is pA; 2.Integrating time is 10ms; 3.range1;): ch1:1341.40 ch2:1341.93pA ch1:1364.61 ch2:1364.79pA ch1:1341.51 ch2:1341.89pA ch1:1341.47 ch2:1341.97pA ch1:1364.60 ch2:1364.68pA ch1:1341.44 ch2:1341.88pA ch1:1364.60 ch2:1364.67pA ch1:1341.49 ch2:1341.97pA ch1:1341.52 ch2:1341.98pA ch1:1364.53 ch2:1364.69pA ch1:1364.58 ch2:1364.67pA ch1:1364.59 ch2:1364.79pA ch1:1341.46 ch2:1341.97pA ch1:1341.42 ch2:1341.89pA ch1:1341.46 ch2:1341.97pA ch1:1364.54 ch2:1364.80pA ch1:1364.62 ch2:1364.69pA ch1:1341.42 ch2:1341.98pA ch1:1364.65 ch2:1364.80pA ch1:1341.44 ch2:1341.99pA ch1:1364.63 ch2:1364.79pA ch1:1364.58 ch2:1364.68pA ch1:1341.48 ch2:1342.00pA ch1:1364.62 ch2:1364.67pA ch1:1341.39 ch2:1341.97pA ch1:1364.61 ch2:1364.67pA ch1:1341.44 ch2:1341.98pA ch1:1341.38 ch2:1341.99pA ch1:1364.56 ch2:1364.78pA ch1:1341.42 ch2:1341.98pA ch1:1364.58 ch2:1364.71pA ch1:1341.46 ch2:1341.94pA ch1:1341.45 ch2:1341.94pA There is fluction still, why? Some one tell me it is because 50Hz power noise. But I think that the 1000ms integrating time should average this noise. Waiting for your help. Thanks
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