Part Number: DAC38J84 Hi, My company is programming the DAC chip directly, without relying on the TI GUI. This method has proven successful with LMK04828 , after only a few answers from the kind folks on ti.e2e.com. The DAC chip appears even easier to control, so we are optimistic of getting on top of the chip in short order. Section 7.3.3 challenges the reader by showing detail of the DACCLK PLL, which is the reference for SerDes PLL, but not the SerDes PLL structure itself. Ultimately, the programmer specifies the SerDes PLL divisors. Absent a diagram of the configuration points (along the lines of LMK manual's figures 12 and 13), it appears that we specify the divisors indirectly, as a function of MPY, Lane Rate (Table 2), and JESD parameter L (perhaps I am overlooking others). Here is the issue: In Section 7.3.3 "SerDes PLL Output Frequency" appears to mean "F_vco." However, the rows in Table 2 make sense when "SerDes PLL Output Cycle" means "frame clock cycle." Would you kindly address the inconsistency? It may be that we have overlooked a pertinent detail in the document. Hopeful thanks --todd
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