Bill, First, I would definitely pull out FB1 and replace it with a short. Ferrites in digital power supplies can cause some unusal problems with supply spiking and maybe it's disrupting the SPI communications. It's probably ok, but it's something to check. I've looked through your schematic again and I'm still not sure what is happening. Conversion timing and reading data shouldn't be affected by any given channel. In your case, it seems that you have problems with input 2, while using battery power and no earth ground. For the ADC it shouldn't matter. I will say that it seems that you have several supply voltages, and I'm not sure how they interact if there are problems on the input. They all seem to share a common ground so I would have imagined that it would be ok. If you are reading the ADC output and the data is the same as the previous conversion, it still seems like a conversion timing issue to me. The only cases where you'd read the same data I can think of are: 1. The data period is longer than expected and the conversion hasn't completed. 2. The conversion didn't start because of an SPI problem and the ADC is still waiting, by re-writing the start command, it comes up. 3. The amount of time that you're waiting to read the data isn't long enough because the OS on-board has the incorrect timing. If you can't poll the DRDY/DOUT to see if the ADC has completed the conversion, then it might be sufficient to plot the SPI communications with an oscilloscope or logic analyzer. By plotting the SPI communication (and you may need a scope with some memory depth), you can see the communication to start the conversion is correct. If you capture that, post it here so that we can review it. Then look at the SPI communication when the read takes place. When the read of the ADC is taking place after the conversion starts, what is the condition of DRDY when /CS first goes low (before the SCLK has started)? If DRDY/DOUT is high, then the conversion hasn't completed. If DRDY/DOUT is low, then you know the conversion has completed. Again, you'd need the 32-bit transmission cycle to make sure DRDY/DOUT goes high when the conversion starts. Get a few scope shots and we can review the SPI timing as well. If the SPI SCLK is too fast, or if the SCLK to /CS is too short, you'll also have problems. Joseph Wu
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