Hi John, Sorry for the confusion. It's not an 'unspecified' timing thing really, it's having the ability to charge the sampling cap in specified acquisition time of the ADC, which happens to be the first three SCLK cycles (see tACQ on page 7) with the ADC128S102 . At the maximum SCLK speed of 16 MHz, that gives you 187.5 ns in which you need to have your input settled on the input cap. This normally means you need to have a low impedance source and potentially a buffer ahead of the mux as depicted in Figure 38. If you go back to the original post, you might notice that Geraldo slowed down the SCLK frequency and saw improvements in the conversion results. This makes sense when you consider that using the slowest SCLK (8 MHz) you now have 375 ns to settle the inputs. Much of this (from a general SAR ADC standpoint) is explained in detail in the TI Precision Labs material I pointed you too.
↧