Hi Jim, I did come across the design for the ADC12DJ3200 on another forum post, and it is how I developed my design. I based my mapping table in the initial post off of that design, and confirmed that my implementation matches its layout. This is why I initially posted this question, as I do not see the correct output after organizing the samples. I wanted to confirm that my issue was not in this area, and possibly earlier in the chain. I find it somewhat odd that the throwaway bits are aligned according to the table. The only samples that appear incorrect are S8-S15, and S24-S31. Then again, these samples may only have an error in the lower 4 bits. However, if this was the case it should manifest in the no signal input. If you have any insight it would be greatly appreciated. Thanks, Steve M
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