Hello Kuramochi-san, Thank you for your post. Yes, it is ok to allow for the power supplies (AVDD and DVDD) to ramp up while /RESET remains low. However, the POR counter will not begin until /RESET is released and CLK is applied. VCAP1 will begin to ramp as soon as /RESET is high. The tPOR delay remains the same - you must wait for VCAP1 >= 1.1 V and 2^18 tCLK periods, whichever is longer. Best Regards,
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