Hi Alex, [quote user="Alexander Smith"]Something else is causing the issue then. DAINY_IN being tied to ground is best practice so that all zeros can be passed (instead of noise) as data if there is an issue, it doesn't explain not getting any data like what you are seeing. [/quote] I thought this might be the case. Hopefully this means we're dealing with a SW issue then. I cannot provide schematics but here is our register table. [quote user="Alexander Smith"]Do you see /DRDY coming out of both devices and are they synchronized? Do you see the same reference voltage on both devices? How many SCLKS are being sent to the master device? Is the dead bit between device data being accounted for?[/quote] /DRDY is only connected to ADS1298 , it is not used in our design as both devices are synchronised with START (or should be) We can measure a reference at the ADS1298 but can measure no potential difference between the VREFP VREFN pins of the ADS1294 . (This seems concerning) We are accounting for the dead bit. Here is a logic analyzer trace of the SPI lines. We can see there is no data on the bus for the last device for the final clocking. I have attached all of these files, including zoomed plots as a zip. Thanks again for the help. (Please visit the site to view this file)
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