Hi David, Thanks for clarifying. I meant to ask about F_RESYNC, whether this bit is set to 1 in both modes, or just one of them. F_DRDY implies that a new conversion result was completed while you were reading old data. It makes sense that the data does not appear corrupted because the output shift register will not overwrite the current data during a read operation (the register map description on page 57 is incorrect - I'm making a note of that now for the next revision). In Asynchronous Interrupt Mode, you should be monitoring the /DRDY pin as an interrupt to your MCU. Between /DRDY falling edges, you must enable the interface and send enough SCLKs to shift out the STATUS word and all the channel data. Use a scope or logic analyzer to see if /DRDY is occurring during an SPI read. I'm still looking for confirmation about whether F_RESYNC can be set to 1 in Asynchronous Interrupt Mode. Best Regards,
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