Hi Jeff, I looks like he is violating the timing specification for this device. Page 5 of the PDS shows that R/W pin must be asserted low before the CS pin is by at minimum 10ns. The CS pin should also go high again before the R/W pin changes states as well. The DATA must be set on the lines before CS goes high again, as it latched on the rising edge of the CS line. Then the R/W line can change after that. Thanks, Paul
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