Hello Eben, thank you very much for your fast answer. The function that bit 0 of address 0x03 (page 0) would mask the PLL alarm explains the behavior that I observed. Could you please answer some more questions and briefly confirm my understanding of the situation. We do get back a value of 0xFC03 when we read an untouched Register 0x0A on page 4. This is confusing. Normally it should be 0xF000 or 0xF003 if I understand the datasheet correctly. Datasheet is "slasea3c - December 2016 - revised july 2017". Page 127: The heading is "Clock Configuration Register (address = 0x0A) [reset = 0xF000]" The corresponding Table 111 shows a reset value of binary 1111 0000 0000 0011 which is 0xF003 By the way. In the table 111 bits 9:2 display a reset value of 0x000 which might be a typo. Here interpreted all 0. So the reset value should either be 0xF000 or 0xF003. This is not what we read out of the register. Could you explain what could be wrong here? Register 0x7F on page 0 gives back 0x8009. This corresponds build version 001 of the chip. Is this alos related to the silicon version you mentioned? The device labeling is DAC38RF83I 73ZCJZ9G1 I did not find the information to mask the PLL alarm in the above mentioned datasheet. Did i oversee this or is this information not included in the actual datasheet? Will there be an update of the datasheet available in the next time? According to your information i understood following: For silicon version PG2 Page 0 register 3 is used for clock masking Bit 0 : PLL Clock alarm Bit 1 : serdes 0 pll or serdes 1 pll alarm Both serdes alarmes are unmasked when bit 0 is set to 1 and bit 1 is set to 0. Thank you very much and best regards Christoph
↧