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Forum Post: RE: ADS131A02: F_RESYNC and F_DRDY bit Errors in STAT_1 Register : Asynchronous Interrupt Mode et Synchronous Slave Mode.

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Hi David, The new data should not overwrite the old data while /CS remains low. Please refer to my earlier post: [quote user="Ryan Andrews"]F_DRDY implies that a new conversion result was completed while you were reading old data. It makes sense that the data does not appear corrupted because the output shift register will not overwrite the current data during a read operation (the register map description on page 57 is incorrect - I'm making a note of that now for the next revision).[/quote] Best Regards,

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