Forum Post: RE: AFE5805 LVDS TEST PATTERNS and LVDS receive

Hi,Chuck,

I use Altera IP altlvds_rx to receive lvds data from AFE5805, deserialization factor is 6, write the rx_out[5..0] into FIFO with rx_outclock(100M), and read from FIFO using 50M clock to splice a 12-bit data. Input some pulses on rx_channel_data_align[0] to realign byte order. I watch the FIFO output signal in Signal Tap, and the result is showed in the figure above. As you suggested, I try the toggle with two codes 0xAAA and 0x555, the phenomenon is the same. I also slow down the input clock of AFE5805 to 15M, there is still no improvement.

Thanks!

Haiteng