I took the codes from TIDA-00648 . then edit it for msp432p401R . I will check with logic analyzer and let you know. void DAC161_Write_Regs (unsigned short *writeValues, unsigned char startReg, unsigned char lengthBytes) { unsigned char outData[3]; outData[0] = DAC161_SPI_WRITE_CMD(startReg); // Switch Endianess outData[1] = *writeValues >> 8; outData[2] = *writeValues & 0xff; USCIB0_SPI_write (outData, RcvData, lengthBytes+1); // Add 1 to length for command byte } void Setup_DAC161 (unsigned short errConfig, unsigned short errLow_uA, unsigned short errHigh_uA) { unsigned short errValue; DAC161_Write_Regs (&errConfig, DAC161_ERR_CONFIG_REG, 2); errValue = DAC161_CONVERT_ERR_VALUE(errLow_uA) & 0x7f00; DAC161_Write_Regs (&errValue, DAC161_ERR_LOW_REG, 2); errValue = DAC161_CONVERT_ERR_VALUE(errHigh_uA) & 0xff00; if (errValue CTLW0 |= EUSCI_B_CTLW0_SWRST; // Enable SW reset EUSCI_B0->CTLW0 |= (EUSCI_B_CTLW0_SWRST + EUSCI_B_CTLW0_MST + EUSCI_B_CTLW0_MSB + EUSCI_B_CTLW0_SYNC + EUSCI_B_CTLW0_CKPH ); // SPI Master, 3 wire, synchronous mode EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SSEL__SMCLK; // SMCLK EUSCI_B0->BRW = 8; EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST; // Clear SW reset, resume operation } void USCIB0_SPI_write (unsigned char *outData, unsigned char *inData, unsigned char length) { unsigned char i; // CS Active Low DAC_CS_PORTOUT &= ~DAC_CS_N; //__delay_cycles(100); // Pause a bit for (i=0; i IFG & EUSCI_B_IFG_TXIFG)); // USCI_B0 TX buffer ready? //__delay_cycles(100); // Pause a bit DAC_CS_PORTOUT |= DAC_CS_N; } unsigned char USCIB0_SPI_writeByte (unsigned char data) { while (!(EUSCI_B0->IFG & EUSCI_B_IFG_TXIFG)); // USCI_B0 TX buffer ready? EUSCI_B0->IFG &= ~EUSCI_B_IFG_RXIFG; // Clear RX Interrupt flag EUSCI_B0->TXBUF = data; // Place data in TX Buffer while (!(EUSCI_B0->IFG & EUSCI_B_IFG_RXIFG)); // Wait for end of data receive return ((unsigned char)EUSCI_B0->RXBUF); }
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