Thanks Tom, With CONVST -> 1 at the next riding SCLK edge the conversion will start. We were planning to wait until this is complete before RD->0. We actually wanted to read the signal immediately after the conversion is complete. With the combined CONVST_RD ->1 signal the conversion would start and once complete with the CONVST_RD->0 we want to read the data. According to the picture on page 30 of the datasheet this should be possible. The question would be how many SCLK cycles do we have to wait until before the read register has been updated. thanks Lutz
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