Eben, Please see below customer feedback: We are now passing the short pattern test. But the spectrum is indicating a problem (as if I and Q delays are not matched). The datasheet for the DAC doesn’t provide much insight to the internal architecture and/or associated control. Looking for suggestions … Another question is the JESD RBD buffer one and the same as the JESD FIFO? Note: delay differences might be per JESD lane
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