Part Number: ADS1115 Hi, I am looking into an BMS system issue and have a few technical inquiries regarding the ADS1115-Q1 reset design. For the ‘power-down state’ in datasheet, the ADS1115-Q1 does not perform A-to-D conversion but digital interface would response to I2C master communications, right? When the VDD of ADS1115-Q1 ramping up from 0 to the recommended range, what's the voltage threshold for the start of internal reset process? How long would it take for ADS1115-Q1 transiting to the power-down state after threshold hit? Also, when there is a down-slope transient on VDD, would there be any hysteresis for this threshold and any changes to the reset process? Great thanks for your help!
↧