Hi Keith, I added the 0.1uF caps to the DVDD and AVDD pins and a 47pF cap to the CONVST pin. The cap on the CONVST pin appeared to prevent the erroneous conversions. I had to add another 47pF cap the the SCLK pin, as a similar issue occurred: each rising edge of DOUT coupled a pulse into SCLK, clocking out an additional bit. To reduce ringing, I placed 499 Ohm resistors in series with the SCLK and CONVST lines. I'm having some issues with stability of the digital output: of the 18 bits, only 8 remain constant for a DC input. I think this is a separate issue, and I'll plan to ask a separate question if I'm not able to solve it. Thanks, Wes
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