Hi, You will need to read back alarms config100 to config108 to see if there are any errors with each JESD lane. Please be sure to clear the alarms before reading them to see the latest alarm. Typically, you may see 8b/10b not in table and 8b/10b disparity error. If such error occurs, then you will need to check the signal integrity of your setup, particuarlly the FPGA. The TSW14J56 + DAC38j84 EVM can run up to 12.5Gbps without much issue. I suspect you may first need to elevate the serdes swing of your FPGA output to improve the signal integrity. This may cause link stability issue. Please also review the JESD204B document available on the JEDEC website free of charge for the physical layer debug. -Kang
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