Mhed, There are no test bench files for the Verilog modules in the J56 firmware, so the released firmware can’t be simulated directly. If you developed test bench files for different modules but are facing issues with Model Sim, 1. Can you first compile the J56 source code with no test bench files included to verify all other files are available. 2. Please note, project file names in the released firmware source are a bit long, so we have to ensure the firmware file path + file name is short enough to restore the project successfully. Please keep the path of the firmware file short, with minimal sub folders before restoring the project in Quartus. This should help. 3. If there are any issues still, please share screenshots of the compilation error. Attached is a design document developed for the J56 firmware. This is a good starting point for understanding and editing the code. Regards, Jim (Please visit the site to view this file)
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