Hi Jim Thank you for your answer. I'm going to read the document you've attached. Ok for the testbench, too bad it would have helped me a lot in my work. However, even if there is no testbench, when you launch RTL simulation flow from Quartus, the source code is compiled first. And this is during this step that i've got errors. I don't have errorr if i run "analysis & synthesis" so i thought that the problem is in compilation script for Modelsim (jesd204b_run_msim_rtl_verilog.do or jesd204b_run_msim_rtl_vhdl.do) And, yes i as it is mentionned in other posts, i'had rename the projet to limit the number of characters.
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