Aditya, The Altera chip is programmed as soon as power is applied. The CPLD code has not been tested for this mode and may have an error in it. The source code is attached. You can also verify the I/O levels with this code. Are you programming the LMK for 4 wire mode? By default, this part comes up in three wire mode. You would need to set bit 4 to a "1" in address 0x00 for this. You also need to program register 0x14A to 0x33 for the read back to work properly as well. Regards, Jim (Please visit the site to view this file)
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