HI, as you wrote in last post, I check the power sequence for clock and the ADC. The ADC power 1.8V is almost 7 ms earlier compared to clock to be present for ADC. Pls check the Plot below. As you said I will confirm the probe impedance for both. I will upload the Plots with 100E termination on clk. Regarding boards, Even the third board which was working, now have same status. The details are : Board 1 and Board 2 - ADC output clk - CLKOUTp is present "100MHz", CLKOUTn - "Not present" Even then some how (may be as I am using differential LVDS receiver buffer inside FPGA), I am getting clk inside FPGA. because of which a function test is passing at present. But Note that still CLKOUTn is not present on Board 1 and Board 2. Board 3: Both ADC CLK p & n are continuously changing. they are not stable at 100 MHz. Kindly comment.
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