Hi Ian, Take a look at section 7.5.3 in the datasheet which describes two data transfer time zones (Zone 1 and Zone 2). Zone 1 is the standard SPI transfer zone; Zone 2 is referred to as part of Enhanced SPI. MultiSPI refers to multiple SDO lines, but can also be thought as part of 'enhanced SPI' as well. Basically, Zone 2 allows a larger percentage of the cycle time to be used to read data out of the device, which lowers the SPI SCLK speed requirements. Reading in Zone 2 is controlled by the host timing (SCLK relative to the /CS, CONVST edge). MultiSPI requires writing to the configuration registers to enable multiple SDO lines (1x, 2x, 4x). There is a good White Paper that describes all of this in more detail. http://www.ti.com/lit/wp/sbay002/sbay002.pdf The table on the front page of the datasheet is approximate and assumes a single SDO line reading in Zone 2. Use the values in section 6.6, Timing Requirements, and equations 8 and 9 in section 7.5.3, to calculate the exact minimum SCLK frequency for different sampling rates. Example: Fsample=800kHz Tsample(Tcycle)=1250nS Tread-z2=1250nS-20nS-30nS=1200nS (equation 8) Fsclk=16/1200nS=13.33MHz for 16b data transfer (equation 9) Fsclk=18/1200nS=15MHz for 18b data transfer (16b data plus 2 parity bits) It never hurts to include a 10ohm series resistor in each digital line. This helps with high speed digital edges that could couple additional noise into the ADC. Depending on the FPGA used, you can usually slow the edge rates down. The ADS8920BEVM evaluation board has resistors, but just uses 0 ohm jumpers. I suggest using the EVM design and layout as a good starting point. http://www.ti.com/lit/ug/sbau270/sbau270.pdf Sharing the digital lines (except SDO) between multiple ADS8920B devices will not be an issue. The only limitation is that each device will be configured identically. Regards, Keith
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