Part Number: ADS1293 I have 2 questions on the ADS1293 . 1.I am planning to run with an external clock for noise issues, are there any internal clocks that are not slaved to the CLK input that might cause noise issues? 2. Is it possible to run without the DRDYB signal without loosing data? ie how big is the buffer and is the information available in a register to poll? so is there another way of detecting there is good data and if we miss a data ready how long do we have before the data is stale. if it helps we plan to run the SPI bus at a multiple of the CLK drive. thanks tim
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