Hi Navdeep, Thanks for your post and welcome to the forum! I am not familiar with your simulator, but is there a connection for the RLD to reject the common-mode noise from the mains power? Is it possible for your to verify the frequency of the noise in the time domain? If you are collecting data before the SinC filter resets, then yes the system is more susceptible to noise. Additionally, since the datarate drops in single-shot mode, the rate that the ADC is decimating decreases, and more noise will make it through to the conversion result. I am not sure why you are unable to see /DRDY toggle. Have you confirmed that /DRDY is not toggling by probing the device pin with an oscilloscope? This post: e2e.ti.com/.../2727329 contains my standard SPI interface debug checklist. Please take a look and verify that you can correctly use the SPI interface.
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