Michael, Per the datasheet this configuration is allowed, however I would call out the comments on page 8, also pasted below: "The serial clock is limited to one-tenth of the master clock frequency. For a 2.4576MHz master clock, the serial clock may be no faster than 254.76kHz. The designer should bear this in mind, as it may prevent the DAC1220 from being shared with other SPI devices or placed on an SPI bus, which may run much faster."
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