Michael, Though I have not tested this myself, I do not see any reason why it would not work. Page 11 indicates that when CS is high all activity on SCLK is ignored by the device, so from the DAC1220 perspective it should not be impacted when interfacing other devices. Though it is not explicitly stated, I believe the default state of the SDIO pin is high-z, basically in input mode, so the DAC1220 would not impair other activity on the bus either. SDIO is only driven by the DAC1220 when a register read is performed, which would imply the DAC1220 CS pin is driven low. I am basing this assumption on the last paragraph on Page 8 in the "Serial Interface" section.
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