Thanks for the replies. The level shifter pin is high (thereby releasing the inhibit) and the FPGA pins are definitely setup as inputs. The problem is the signals between U25 and U27 however, so I'm not sure if the status of the FPGA pins is relevant. As Alex alludes to, the output pins (Y3 and Y4) are always high, as I would expect given that the input side signals never drop below the low voltage threshold. This is pretty much exactly the problem: the input pins effectively never go low, even though the ADC logic wants them to be, so the output pins are always high. No testing the part independently unfortunately isn't really possible. Please let me know what you find. I was thinking of adding a pull down of 100R or so on each signal line and seeing what that does.
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