Dallin, There are many things that can impede communications to the device. To debug any kind of digital communication, there are several things I would try. First, I would certainly use an oscilloscope or logic analyzer to view the communication lines coming out of the device. This is the fastest way to ensure that the communication waveforms coming out of the master are as you expect. You can also verify the digital timing. If you can view this, and are still having problems, you can post the plot back in this thread. One quick check would be to verify the mode of SPI used to communicate with the device. This device uses CPOL=0 and CPHA=1 for the SPI, meaning that the SCLK dwells low at idle, and data is clocked in at the falling edge of the SCLK (you can see this in figure 1 of the datasheet and you should verify that the communication looks like this as well). I would then check to see that START, /RESET, and /PDWN are all high when using this device. If the device is operational and converting, I would check the /DRDY pin also. There should be a small /DRDY indication for each completed conversion. I think this device operates at a default of 8kSPS, so there should be a narrow /DRDY pulse every 125us. Instead of reading data, you may also try reading from the registers instead. For the RREG command, you should be able to read the registers, which should be a known default value at start up. If you can read from the registers, then I would check the WREG to write to the register and confirm that you are able to do that also. Joseph Wu
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