Hi Henry, Please see attached for some basic training for DAC38J84 . During your recent travel to Dallas, we also have detailed JESD204B training, including alarm handling. You may revisit those slides as well for additional training. They will apply to the DAC38J84 . There are two mechanism for the SYNC signal delivered from the DAC38j84 to the FPGA. One is the Error Reporting (lasting about 2 Frames) and another one is SYNC Request (5 frames + 9 octets in length). Error reporting is simply (set by the user) to report non-critical errors that do not disturb the link, but the DAC should still let the FPGA know that some problems happened before. SYNC request is basically to indicate that the link has been lost, and the FPGA should resend K28.5 handshaking characters to reestablish the link. In general, the JESD204B closed loop will try its best to recover the link by itself through handshaking SYNC signal and the transmission of k28.5 characters. In critical overall errors such as loss of PLL lock or SERDES PLL lock, then the user will need to intervene externally. To disable the error reporting of the link configuration, you may simply set the ERROR_ENA_LINK0, bit 5 to zero to ensure the link configuration (i.e. ILAS sequence check) do not prompt for the triggering the SYNC pulse for 2 frames. (Please visit the site to view this file)
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