Hello Kiran, The 0.8Vpp specification of the DAC38j84 clock input is a typical recommended clock swing for optimal SNR/SFDR. It is defined as differential (P - N leg) swing. This specification is the same as the VOD specification of the LMK04828 (see figure 9 for VOD definition). The standard LVPECL termination (121ohm pull-down) is sufficient for the application, and also, you have to compensate for PCB loss and potentially clock filter loss and reflections. Hence, the swing required at the clock driver side may need to be slightly higher depending on PCB design. See below specification of LVPECL for VOD specification.
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