Hello Bartosz, You are correct; there are no registers to program in this part. You just need to connect the different configuration pins high or low for the different modes of operation. The following will configure the device for high-speed mode, with SPI, TDM, on single DOUT1 line for all 8 channels. With CLK at 27MHz, the output data rate (and frequency of /DRDY) should be 105.5kHz. I suggest measuring each pin to confirm it is at the proper level. IOVDD, 1.65 to 3.6V DVDD, 1.8V AVDD, 5V VREFP, 2.5V VREFN, 0V (Connect to ground) AGND plus PowerPad to ground AVDD should rise up after IOVDD/DVDD, if not, may want to pulse the /SYNC pin low for >1fclk. NOTE: AGND, DGND, VREFN, should all be connected to the PowerPad and the PowerPad should via into the system ground plane. CLK (Input) -> Should be continuous 27MHz or less, referred to IOVDD level. CLKDIV (Input) -> connect to IOVDD DIN (Input) -> connect to GND DOUT1 (Output) -> Output Data /DRDY (Output) -> Should be repetitive at fSample, 105.5ksps with CLK=27MHz FORMAT0..2 (Inputs) -> Connect to GND for SPI, TDM, Dynamic MODE0..1 (Inputs) -> Connect to GND for High Speed mode. /PWDN1..8 (Inputs) -> Connect all 8 inputs to IOVDD to enable converters. SCLK (Input) -> SPI Clk input, maximum frequency equal to CLK (27MHz) /SYNC (Input) -> Either connect high or toggle after power-up to reset/re-synchronize the internal counters TEST0..1 (Input) -> Connect to GND If preferred, you can connect /PWDN2..8 to GND to shutdown all channels except for Channel 1. This may make it easier to debug the SPI communications. I hope this helps. Regards, Keith N. Precision ADC Applications
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