Hey, thank you for the thorough reply. We set the NDM bit to logic low '0' - DEMUX mode (i.e. We use both DI and DID for sampling the I channel). About the sampling logic, as mentioned, the TPM mode works fine all the time, even when the data is corrupted. Therefore Im pretty sure that the LVDS mechanism work fine. I wanted to ask some more specific questions about the power-up sequence (following your recommended one): Apply power to the ADC - I cant control the timing of the power-up. The device is fed straight from the board. Can it be a problem? Configure all of the control pin inputs to the desired settings - Following the comment from (1), I cannot assure that the device "wakes up" where all its pins are at their final state. Turn on the ADC clock - We use external pll devices which feed the device with fSample/4 clocks. Should I keep PDI and PDQ at logic high '1' as long as the plls are not locked? can it be a problem? Configure all of the configuration register settings as needed per datasheet and application needs. The order of writes is not critical. - About "The order of writes is not critical." : even the timing of the writing to CAL? Shouldn't the first register be written last? Perform an on-command calibration, initiated by CAL pin or CAL configuration register bit. Enable the FPGA data capture logic If ADC temperature shifts by more than 20-30 degrees then perform an on-command calibration Thanks again for replying. Itay
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