Hello Itay I have copied your comments and questions here along with my responses: We set the NDM bit to logic low '0' - DEMUX mode (i.e. We use both DI and DID for sampling the I channel). About the sampling logic, as mentioned, the TPM mode works fine all the time, even when the data is corrupted. Therefore I'm pretty sure that the LVDS mechanism work fine. Can you send me the raw data on each ADC output port for TMP mode and for normal data mode with a very low frequency input sinewave signal? Perhaps something like 10 MHz? In my experience if the TPM data is in the correct order and is aligned correctly across the output ports, then the sinewave data should be OK as well. Using a low frequency sine helps to ensure the port data is properly aligned. I wanted to ask some more specific questions about the power-up sequence (following your recommended one): Apply power to the ADC - I cant control the timing of the power-up. The device is fed straight from the board. Can it be a problem? This is probably OK. Is the ADC powered up before, after or at the same time as the following items: ADC logic control input drivers ADC clock source In general the ADC should be powered up either before or at the same time as the logic control input levels are applied. Configure all of the control pin inputs to the desired settings - Following the comment from (1), I cannot assure that the device "wakes up" where all its pins are at their final state. Turn on the ADC clock - We use external pll devices which feed the device with fSample/4 clocks. Is the applied ADC clock signal 1800 MHz or a lower frequency? Are these other clocks at fSample/4 used for the Should I keep PDI and PDQ at logic high '1' as long as the plls are not locked? can it be a problem? These don't need to be held at logic 1. The device can be active while the clock starts up. Configure all of the configuration register settings as needed per datasheet and application needs. The order of writes is not critical. - About "The order of writes is not critical." : even the timing of the writing to CAL? Shouldn't the first register be written last? Yo are correct, the CAL bit should be written last. The CAL process should happen after all logic control pins are set, and all other registers are configured, with stable clock and a device operating temperature near the final expected temperature. I hope this is helpful. Best regards, Jim B
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