Hi Bob, Thanks for the response! The higher amplitude in DOUT signal got fixed after adjusting the external clock to 0V to 5V. We have one more query! Whenever the last bit of DOUT is high, the signal gets decayed slowly. I have attached the captures for your reference. ----- Capture details:- We are trying to read the register having value 0Fh. Since the last bit of the register is one, the DOUT is getting decayed. But still we could infer the value as one, as the signal at DOUT remains high at the falling edge of the SCLK. Could you please explain the above behavior. Our Configuration, AVdd = DVdd = 5V. SCLK = 1KHz, Fosc = 2.4576MHz(through function generator), Fmod = 19.2KHz, Fdata = 10Hz. Thanks and Regards, Makesh
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