Hi Uchikoshi-san, I discussed this today with a digital designer and our recommendation is to try and keep the duty cycle to min 40% and max 60%. In addition to the setup and hold times, there may be some propagation delay between DIN and DOUT which may necessitate the need for some normal duty cycle of SCLK. Most SPI peripherals should provide an SCLK with 50% duty cycle, but if this is not possible (for example in the case that SPI communication is implemented via bit-banging) then the SCLK frequency may need to be reduced. Unfortunately, I do not have any simulation or characterization on this particular parameter to be able to give more specific advise.
↧