Part Number: ADS7043 Hi, As per the DS7043 Data sheet, Figure1 timing diagram mentions that the Tconv (conversion time) is 12.5 × tSCLK + tSU_CSCK. for eg: in my design if i use 100KHz as sclk, then 12.5*10us+15ns = 125.15us the conversion data spi shall be available after 125.15 us T.e after ~13 clocks. but in the diagram the Data for sample is mentioned as N during the the conversion time. Please confirm the data available in the tconv time is the Data for sample N-1 or Data for the sample N is valid after 2 cycles after the chip select goes low.
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