Hey Ryan, Thank you a lot, that really helped. I eventually realized that the current Rf and Cf values for setting the bandwidth of the RLD loop is set at 40hz, according to the equation fBW = 1/(2 pi Rf Cf). Since my setup is in congruence with what you suggested, I believe I will need to adjust the resistance and capacitor values to actually include the 50hz value that I am working with. I hope that this is the correct thing to do, I will update you if that turns out to be the solution. Also please let me know if I misunderstood the schematics/equations from the manual and the RLD file, or if my decision to change the resistance and capacitance values will not have the desired effect.
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