Hi Alex, Before feeding the clocks from TIDA-01021 clocking board to ADC EVMs, check the clock skew (DCLK-to-DCLK and SYSREF-to-SYSREF) in oscilloscope and use the length matched cables for clock feed as well as clock skew measurement. Please follow the HW set up and SW set up (programming sequence) videos for TIDA-01021 mentioned in the below video link, which may resolve the trigger timeout error. Get Your Clocks in Sync: Hardware Setup Get Your Clocks in Sync: Software Setup Regarding the inconsistent delay, it seems trigger is not happening at correct instant or SYSREFs are not align. Hope, the above mentioned programming sequence would resolve both the issues. Regards, Ajeet Pal
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