the LVDS voltage depends on driving current vs termination R. in past TI ADCs, we assume +/-3.5mA @ 100ohm load. it appears to be 0.7Vpp. when driving current is reduced, LVDS votlage is reduced as well. of course, the driving capability will be less.
0.3Vpp to 0.35Vpp LVDS can work as well from our experience.
as our datasheet shows, AC coupling is required considering the 1V VCM votlage. DC cuopling can be applied only when the LVDS driver's VCM is the same as AFE's.
LVDS is terminated at 100ohm deferentially by default. so you can use 100ohm diff impedance in PCB layout. some FPGA venders have different internal term R values. you can discuss with FPGA venders.
Thanks!