Hello Mr. Taichi,
My response below:
Q: That is, this device can accept LVDS with no CLK?
A: No, the LVDS output data uses TXCLK as clock, as shown below.
Q: What is ”12 Pin to 16 Pin (Selectable) LVDS Serializer" on datasheet_P1 meant?
A: The 5 pair (10 data + 2 clock pins or 12 pin) and 6 pair (12 data + 4 clock pins or 16 pin) modes are two selectable LVDS output formats selectable using this register (0x01 Hex) bit [2:0], as shown below. Table 13 (Bit Formats) shows more details about each mode. Figure 2 (Example Circuit) shows the schematic for 16 pin setup.
From datasheet page 38:
LVDS Data Output
AFE data is output on a serialized LVDS interface. Several different serializing modes are available, with 5 or 6 pairs used for data transfer.
6 pair modes allow the use of the standard, DS90CR218A, or DS90CR364 deserializer ICs.
5 pair modes permit usage with a single 5 channel deserializer. In this mode, the unused data pair can be left open circuit to minimize power consumption and component cost. Also, to maximize layout flexibility, both TXCLK pairs are active. The unused TXCLK pair can be left open circuit to again minimize power consumption.
Regards,
Hooman