Hi Dean and thanks for your msg, I think i have finally concluded which parts to use. I am focusing on clock oscillator LMK61E2-125M designed for 125MHz and the 4-LVPECL-output clock buffer CDCLVP1204 . This started with me knowning almost nothing about what the challenges were when it comes to clocking a 12bit ADC. I went through a lot of TI app notes and i think now that things are much more clear. Finally i think that these part are the suitable candidates for not comprimizing the SNR of the the ADC ADS4225 that i have selected. I really did not know at first that these parts even existed as i never got involved with the design of high speed stuff. So, talking to Dan, our last conversation was about me using a 4-output clock with a ~300fs RMS phase jitter which combined with the 140fs aperture jitter resulted in a ~330fs phase jitter which is close to the max allowable phase jitter that i calculated @ 380fs (Fin:100MHz). In order to improve the clock phase jitter performance i finally selected the LMK61E2-125M with a TYP 100fs @ 125MHz and CDCLVP1204 with an additive phase jitter of ~55fs. So considering this information i am well below the 330fs performance of my previously selected components. I have been also thinking about using very narrow ~20KHz crystal band-pass filters to further reduce jitter but that is (after searching a bit) difficult to find. Also slew rate would have to be improved due to the fact that the signal would end up being a pure sine. My questions regarding the currently (newly) selected compnents are: How do you add all phase jitter values of ADS4225 (aperture jitter: 140fs), LMK61E2-125M (100fs) and CDCLVP1204 (55fs). The word "additive" keeps me thinking... If i had to guess it would be this: Also regarding the ADC ADS4225 , i have got a few questions: I am considering using the mux mode in the output which means that with a 125MHz clock, ADC's parallel B output would be 250MHz. I am a bit confused at this point... Can i use both mux mode to get both inputs in one parallel output and at the same time use DDR LVDS to pass the data to the FPGA? Using the FPGA's LVDS receivers would be the only way to pass that data into the FPGA, otherwise its' pins would only be capable of switching up to 90-100MHz As this ADC is going to be used as a DSO, i have to find an extremely low noise opamp with a high input impedance. Which one would you recommend? The input DC reference voltage is nowhere to find. Usually there is a pin where i can supply a high precission DC reference which defines the LSB level. However, i saw that 2Vpp is the max input voltage. Is that supposed to be considered the internal voltage reference? The input of the ADC (P53, 9.3.1.2) refers only to AC coupled topologies. I understand that this ADC is supposed to be used in SDR applications but shouldn't there be any references to DC coupling topologies? Would such an implementation pose a threat to the DC accuracy behaviour? Thanks again for the help. Manos
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