Part Number: ADS1672 Dear, All Customers are using the ADS1672 . Multiple ADS1672 are used but simultaneous sampling is necessary. For this reason, I have the following questions. Furthermore, they use the mode of "SCLK_SEL = 1". a. Under the following conditions, can each ADS1672 be guaranteed to sample on the same CLK edge? - Connect the same CLK to the CLK terminal of each ADS1672 . - Enter the START signal by observing the specified value of "Figure 3. START Timing". b. They want to know the CLK edge that output DRDY to see if the ADS1672 was sampled on the same CLK edge. Therefore, I want to know the Max value of the DELAY value from CLK to DRDY. Please tell me the Max value of Tclkdr. If it can not be guaranteed, the assumed value (design value etc) is also good. The questions in b. are necessary to determine the maximum frequency of the CLK they can use. Please tell me these two. Thanks, Masami M.
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